Computer Architecture and Performance Modeling
How Hardware Shapes Computation
Core Themes
Performance is governed by instruction-level parallelism, cache hierarchies, branch prediction, vectorization, memory bandwidth, and accelerator support. The same algorithm can behave very differently across architectures.
Important Terms
What is the practical significance of cache locality?
Better locality increases the chance that needed data is already near the processor.
Correct answer: It reduces memory access latency and improves throughput
Why can a theoretically optimal algorithm still be slow on real hardware?
Asymptotic complexity does not capture all hardware effects.
Correct answer: Because constant factors, memory access patterns, branching, and vectorization affect actual performance.
Compute-Bound vs. Memory-Bound
Compute-bound
- Limited by arithmetic throughput
- Benefits from vectorization and faster ALUs
- Often found in dense linear algebra
Memory-bound
- Limited by data movement
- Benefits from locality and caching
- Common in graph and sparse workloads
Performance Modeling Workflow
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1
Identify the dominant bottleneck: compute, memory, or communication.
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2
Measure instruction mix and data access patterns.
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3
Use a model such as roofline to estimate ceilings.
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4
Optimize data layout, vectorization, and parallelism.
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5
Re-measure and confirm that bottlenecks shifted as expected.
A workload that is limited mainly by memory bandwidth is called what?
Memory-bound workloads spend most time waiting on data movement.
Correct answer: Memory-bound
Engineering Principle
Performance tuning is often about reducing data movement rather than increasing arithmetic speed.
Advanced View
At scale, architecture-aware algorithm design blends numerical analysis, systems profiling, and hardware counters. This is increasingly important on heterogeneous machines with GPUs, tensor units, and deep cache hierarchies.